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Irish Expert Taught The Tricks Of Digital Design To GEC Students In Vaishali, Workshop Will Run Till 22

M
Md Amir
Contributor
February 17, 2026

Samvad Sutra, Jagran, Bidupur. An important initiative has been taken towards technical skill development in the Government Engineering College (GEC), Vaishali, located at Chaksikander in Bidupur block.

A weekly workshop on the topic Verilog for Beginners has been organized by the Department of Electronics and Communication Engineering of the college.

The objective of this workshop, which will run from 16th February to 22nd February, is to equip the students with modern technical knowledge. The workshop was inaugurated by convener Prof. Priyanka Jha, Coordinator Prof. Prerna and Prof. It was done by lighting the lamp in the presence of Neha Chaudhary, Head of the Department Dr. Ravi Ranjan and other faculty members and students.

Addressing the function, Principal of the college, Dr. Ananth Kumar said that this workshop will prove to be a milestone in developing the technical and practical skills of B.Tech students.

He stressed that this step of the department will be helpful in creating new employment opportunities for the students. Head of the department, coordinators and coordinators gave detailed information to the participants about the curriculum of the workshop, its usefulness and the outline of the upcoming sessions. In the program Prof. Irfanul Haq, Prof. Nivedita Singh, Prof. Kumar Vimal, Dr. Tripta and Prof. Sunaina and other faculty members were present.

Qualcomm experts connect online from Ireland

On the first day of the workshop, Rahul Ranjan, Senior RLD Design Engineer, Qualcomm from Ireland, joined online as the keynote speaker.

He gave a detailed discussion on the topic Verilag for Beginners and shared precise information on technical aspects like modules, data types, levels of modeling and syntax. The students seemed very excited after interacting directly with the expert.

Informed about the nuances of digital designing

Workshop coordinator Prof. Priyanka Jha told that Verilag mainly has three modeling levels – behavioral, dataflow and structural and gate-level. These levels allow any digital design to be defined from high-level details down to straightforward gates.

He said that its practical knowledge is extremely useful for the career of the students. Coordinators said that only those regularly successful students who have at least 95 percent attendance in the workshop will be awarded certificates.

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